This invention relates to content addressable memories (CAM's); and more particularly, it relates to the overall architecture and functional capabilities of such memories.
By a content addressable memory is meant an electronic module which contains: 1) a plurality of address registers, each of which holds a word of data herein called a compare address; 2) a write circuit which selectively loads the compare addresses into the address registers; 3) input terminals for receiving sequences of other data words herein called search addresses; and 4) respective compare circuits which are coupled to each of the address registers and the search address input terminals. In operation, the content addressable memory compares each search address via the compare circuits to the compare addresses in all of the address registers. If a search address equals a compare address in one of the address registers, then a MATCH signal is generated that indicates which of the address registers caused the match.
This MATCH signal is then utilized to perform some higher level operation. For example, the content addressable memory can comprise a portion of a data cache in which the MATCH signal is used to read data stored in the cache. If no MATCH signal occurs when the search address is sent to the content addressable memory, then the content addressable memory and the cache are updated via a write operation. These compare and write operations are cyclicly performed in synchronization with a clock.
In the prior art, various references teach and describe transistor circuits by which the content addressable memory can be implemented. For example, see an article entitled "Design, Selection and Implementation of a Content Addressable Memory for a VLSI CMOS Chip Architecture" by S. Jones in the IEE Proceedings, Volume 135, Pt. E, No. 3, May 1988, pages 165-172. There, the circuit design and characteristics of four different content addressable memories, labelled CAM A thru CAM D, are disclosed and compared in terms of speed, power dissipation, and chip space.
Despite such prior art, the present inventors have discovered a new overall architecture for the content addressable memory by which its speed of performing the search and write operations is substantially improved. As a result, any higher level function in which the CAM performs a role is also similarly improved.